The material is structured into two main parts: developing test environments and implementing testable hardware. Key Topics Covered
Memory fault models, MBIST (Memory BIST) methods, and functional procedures.
It utilizes Verilog models and testbenches to implement fault simulation and test generation algorithms. Digital System Test and Testable Design: Using ...
Logic BIST basics, test pattern generation, and output response analysis.
Scan architectures, RT-level scan design, and Boundary Scan (JTAG). The material is structured into two main parts:
Verilog is used to describe the internal architectures of Built-In Self-Test (BIST) and Design for Testability (DFT) . This helps engineers evaluate hardware overhead and timing feasibility, which is critical for System-on-Chip (SoC) designs.
Random and deterministic test generation methods, plus sequential circuit test generation. Logic BIST basics, test pattern generation, and output
Are you interested in a specific from the book, like BIST or Boundary Scan , for a more detailed breakdown? Courses Syllabus – Monsoon 2024 - pgadmissions@iiit.ac.in